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Digital Circuits and Microprocessors

Semester 1

The main objective of this course is to familiarize students with digital circuits and systems and in particular, the internal operations and design of microprocessors – Reduced Instruction Set computers (RISC) and Complex Instruction Set Computers (CISC). Basic processor designs will be covered, including Sequential Logic and Memory Design. Having set a good foundation, advanced processing techniques such as Microprogramming, Cache Memory Management and an introduction to parallelism will be covered.

The learning experience is enhanced with computer-based exercises and assignments. The assignments will include: (1) a take home problem solving questions design to test student understanding of the theory; and (2) a report in the form of an IEEE paper structure on a survey of the state-of-the-art in digital circuits and systems. The intent is to expose the student to high level technical publications. Circuit simulation tools will be used throughout this course.

Syllabus: 

Digital Logic Design: Brief review of Combinational logic; Flip-Flops and Latches: Synchronous, Asynchronous, Single bit Memory elements, Counters & Shift Registers and Timing; System specification using State Diagrams; System design using state diagrams and flip-flops; The design of multidimensional memory arrays using flip-flops

Computer Arithmetic: Unsigned and Signed Integer Representation; Signed Magnitude Representation; One’s Complement Representation; Two’s Complement Representation; Floating-Point Representation; Fractions; Floating-Point Addition, Multiplication and Division

Processor Organization: Overview – RISC, CISC, Data Path, Control Unit; Operand Types; Addressing Modes; Instruction Types; Instruction Formats– zero, one, two and three address machines; Micro-program Control -  Hardware and Software implementation, Data Path manipulation

Cache memory: Cache Design Basics; Mapping Function - Direct Mapping, Associative Mapping and Set-Associative Mapping; Policies; Write Policies; Cache management - Locating a Block and Replacement Policies

Parallelism:  Pipeline - Basic Concepts; Handling Resource Conflicts; Hazards; Register Forwarding; Register Interlocking; Handling Branches - Delayed Branch Execution, Branch Prediction and Performance Enhancements; Superscalar Processors; Superpipelined Processors; Very Long Instruction Word Architectures; Example Implementations - Pentium and SPARC Processors; Vector processors

Interrupts: A Taxonomy of Pentium Interrupts; Hardware and Software Interrupts; Example implementations – Pentium and SPARC Processors

Evaluation: 

 One 2-hour theory final exam paper – 60%

  Mid Semester exam -   20%

  Assignments                 20%

  • Six take-home problem solving assignment of equal weighting (10%)    
  • One paper on a survey of the state-of-the-art in the analogue circuit designs (10%). Report will take the form of that required for an IEEE paper publication.
Learning Objectives: 

Upon completing this course students should be able to:

  • Construct circuits that  can store a single bit using latches and flip-flops
  • Design more complex sequential circuits such as counters and shift registers using flip-flop.
  • Design electronics circuits using state diagrams to capture specifications and  flip-flops for implementation
  • Construct multidimensional memory arrays,  similar to cache memory
  • Explain the operations and structure of a general microprocessor
  • Explain the operation of the flow control mechanisms used in RISCS and CISC processors
  • Examine the techniques used in micro-program controlled processors by writing micro-programs and showing how the micro-program manipulates the data path
  • Identify and analyze the different pipeline systems  by demonstrating how each system will run a typical set of instructions
  • Illustrate how conflicts and hazards are handled in pipelined systems by examining various scenarios
  • Examine the theory of very long instruction word architectures and simulate the operations of vector processors
  • Examine the operations of cache memory by simulating the different mapping functions with various scenarios of  data request
  • Examine the principle of operation of interrupts  and demonstrate how interrupts are serviced
P14A/(PHYS1411 and PHYS1412) and P14B/(PHYS1421 and PHYS1422) and ELET1400 OR CS11A/COMP1110 and CS11B/COMP1120

Text book:

“Digital Design and Computer Architecture”: by David Money Harris, Sarah L. Harris Publisher: Morgan Kaufmann (2007)

Recommended Readings:

1.      Modern Processor Design Fundamentals of Superscalar Processors by John P. Shen: Publisher: McGraw-Hill Science/Engineering/Math; 1 edition (July 7, 2004)

2.      Digital Logic and Microprocessor Design with VHDL by Enoch O. Hwang: Publisher: CL-Engineering; 1 edition (February 18, 2005)

3.      Fundamentals of Computer Organization and Design, Sivarama P. Dandamudi: Publisher: Springer; 1 edition (January 14, 2003)

Internet Resources:

1.      Java Applet for a basic CPU simulator by Professor Judith Cardell: http://www.science.smith.edu/~jcardell/Courses/CSC103/CPUsim/cpusim.html

2.      Computer System Architecture – MIT  Courseware: http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-823Fall-2005/CourseHome/index.htm

3.      How Microprocessors Work - Howstuffworks.com: http://www.howstuffworks.com/microprocessor.htm

Course Code: 
ELET2430
Credits: 
3 Credits
Level: 
Level 2
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